Altera DisplayPort MegaCore Function - Manual (Page 20)

Packetizer Path
The packetizer path provides video data resampling and packetization, and consists of the following steps:
1. The pixel steer block decimates the data to the requested lane count (1, 2, or 4).
2. The DCFIFO crosses the data into the main link clock domain (
tx_ss_clk
, generated by the
transceiver), which can be 270, 135, 81, 67.5, or 40.5 MHz depending on the actual main link rate
requested and the symbols per clock.
3. The gearbox resamples the video data according to the specified color depth. You can optimize the
gearbox by implementing fewer color depths. For example, you can reduce the resources required to
implement the system by supporting only the color depths you need instead of the complete set of
color depths specified in the DisplayPort specification.
4. The IP core packetizes the re-sampled data. The DisplayPort specification requires data to be sent in a
transfer unit (TU), which can be 32 to 64 link symbols long. To reduce complexity, the DisplayPort
source uses a fixed 64-symbol TU. The specification also requires that the video data be evenly distrib‐
uted within the TUs composing a full active video line. A throttle function distributes the data and
regulates it to ensure that the TUs leaving the IP core are evenly packed.
Note: A minimal DisplayPort system should support both 6 and 8 bpc. The VESA DisplayPort specifica‐
tion requires support for a mandatory VGA fail-safe mode (640 x 480 at 6 bpc).
The packetizer punctuates the outgoing 16-bit data stream with the correct packet comma codes.
Internally, the packetizer uses a symbol and a TU counter to ensure that it respects the TU boundaries.
Measurement Path
The measurement path determines the video geometry required for the DisplayPort main stream
attributes (MSA), which are sent once every vertical blanking interval. Optionally, the IP core can import
a fixed MSA data parameter from an external port, removing the measurement logic. This feature is useful
for embedded systems that only use known resolutions and synchronous pixel clocks.
Blank Generator Path
The blank generator path determines when to send the blank start comma codes with their corresponding
video data packets. This path can operate in enhanced or standard framing mode.
Multiplexer
The IP core multiplexes the packetized data, MSA data, and blank generator data into a single stream. The
combined data goes through 8B/10B encoding and is available as a 20-bit double-rate or a 40-bit quad-
rate DisplayPort encoded video port. The 20- or 40-bit port connects directly to the Altera high-speed
output transceiver.
During training periods, the source can send the DisplayPort clock recovery and symbol lock test patterns
(training pattern 1, training pattern 2, and training pattern 3, respectively), upon receiving the request
from downstream DisplayPort sink.
The source also implements an AUX channel controller, which you access using an embedded controller.
The embedded controller acts as an Avalon-MM master and sends read/write commands to the
Avalon-MM slave interface. The IP core clocks the AUX channel using a 16 MHz clock input (
aux_clk
).
Related Information
Controller Interface on page 4-11
4-4 Packetizer Path
UG-01131
2015.05.04
Altera Corporation DisplayPort Source
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