Altera DisplayPort MegaCore Function - Manual (Page 18)

Source Functional Description
The DisplayPort source has a complete set of parameters for optimizing device resources.
The DisplayPort source consists of a DisplayPort encoder block, a transceiver management block, and a
controller interface block with an Avalon-MM interface for connecting with an embedded controller such
as a Nios II processor. You configure the ports using an RTL wrapper instantiation or by implementing
the IP core as a Qsys component.
Figure 4-2: DisplayPort Source Top-Level Block Diagram
DisplayPort Source
Encoder
txN_video_in
txN_vid_clk
txN_audio
txN_audio_clk
tx_aux
aux_clk
txN_ss
tx_ss_clk
txN_msa_conduit
tx_aux_debug
tx_xcvr_interface
Video Input
Video Clock
Audio Input
Audio Clock
AUX Interface
AUX Clock
Secondary Stream
(Avalon-ST Interface)
MSA Input
AUX Debug Stream
(Avalon-ST Interface
TX Transceiver Interface
Transceiver Management
tx_analog_reconfig
Controller Interface
tx_mgmt_interrupt Interrupt
xcvr_mgmt_clk Transceiver Management Clock
tx_reconfig TX Reconfiguration
tx_mgmt
clk
Avalon-MM Interface
Avalon-MM Interface Clock
TX Analog Reconfiguration
clk_cal Calibration Clock
4-2 Source Functional Description
UG-01131
2015.05.04
Altera Corporation DisplayPort Source
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