Altera DisplayPort MegaCore Function - Manual (Page 98)

Figure 7-5: TX Analog Reconfiguration Waveform
In the timing diagram below,
tx_vod
and
tx_emp
are both set to 00. When the core makes a request,
the
tx_analog_reconfig_req
port goes high. The user logic asserts
tx_analog_reconfig_ack
and
then reconfigures the transceiver. During reconfiguration, the user logic holds
tx_analog_reconfig_busy
high; the user logic drives it low when reconfiguration completes.
xcvr_mgmt_clk
rx_link_rate
rx_reconfig_req
rx_reconfig_ack
rx_reconfig_busy
tx_link_rate
tx_reconfig_req
tx_reconfig_ack
tx_reconfig_busy
tx_vod
tx_emp
tx_analog_reconfig_req
tx_analog_reconfig_ack
tx_analog_reconfig_busy
reconfig_busy
reconfig_mgmt_address
reconfig_mgmt_write
reconfig_mgmt_writedata
reconfig_mgmt_waitrequest
reconfig_mgmt_read
reconfig_mgmt_readdata
00
00
7-10 View the Results
UG-01131
2015.05.04
Altera Corporation DisplayPort IP Core Simulation Example
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