Altera DisplayPort MegaCore Function - Manual (Page 82)

//*********************************************************
// Program VOD Level 1 and Pre-emphasis Level 0 for lane 1
// (DPCD addr=0×00104, data=0×01)
//*********************************************************
bitec_i2c_write(0×58, 0×1c, 0×00); // DPCD addr[19:16]=0×0
bitec_i2c_write(0×58, 0×1d, 0×01); // DPCD addr[15:8]=0×01
bitec_i2c_write(0×58, 0×1e, 0×04); // DPCD addr[7:0]=0×04
bitec_i2c_write(0×58, 0×1f, 0×01); // DPCD data=0×01
//*********************************************************
// Program VOD Level 1 and Pre-emphasis Level 0 for lane 2
// (DPCD addr=0×00105, data=0×01)
//*********************************************************
bitec_i2c_write(0×58, 0×1c, 0×00); // DPCD addr[19:16]=0×0
bitec_i2c_write(0×58, 0×1d, 0×01); // DPCD addr[15:8]=0×01
bitec_i2c_write(0×58, 0×1e, 0×05); // DPCD addr[7:0]=0×05
bitec_i2c_write(0×58, 0×1f, 0×01); // DPCD data=0×01
//*********************************************************
// Program VOD Level 1 and Pre-emphasis Level 0 for lane 3
// (DPCD addr=0×00106, data=0×01)
//*********************************************************
bitec_i2c_write(0×58, 0×1c, 0×00); // DPCD addr[19:16]=0×0
bitec_i2c_write(0×58, 0×1d, 0×01); // DPCD addr[15:8]=0×01
bitec_i2c_write(0×58, 0×1e, 0×06); // DPCD addr[7:0]=0×06
bitec_i2c_write(0×58, 0×1f, 0×01); // DPCD data=0×01
//**************************************************************
// May want to adjust squelch level (DP130 reg=0x03, data=0×08)
//**************************************************************
bitec_i2c_write(0×58, 0×03, 0×08); // 40mV
//***************************************
// Enable EQ (DP130 reg=0×05, data=0×80)
//***************************************
bitec_i2c_write(0×58, 0×05, 0×80);
//*******************************************************************
// Set EQ level to 13dB(HBR2) for lane 0 (DP130 reg=0×05, data=0×85)
//*******************************************************************
bitec_i2c_write(0×58, 0×05, 0×85);
//*******************************************************************
// Set EQ level to 13dB(HBR2) for lane 1 (DP130 reg=0×07, data=0×05)
//*******************************************************************
bitec_i2c_write(0×58, 0×07, 0×05);
//*******************************************************************
// Set EQ level to 13dB(HBR2) for lane 2 (DP130 reg=0×09, data=0×05)
//*******************************************************************
bitec_i2c_write(0×58, 0×09, 0×05);
//*******************************************************************
// Set EQ level to 13dB(HBR2) for lane 3 (DP130 reg=0×0b, data=0×05)
//*******************************************************************
bitec_i2c_write(0×58, 0×0b, 0×05);
UG-01131
2015.05.04
Required Hardware 6-21
DisplayPort IP Core Hardware Demonstration Altera Corporation
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