Altera DisplayPort MegaCore Function - Manual (Page 49)

Controller Interface
The controller interface allows you to control the sink from an external or on-chip controller, such as the
Nios II processor for debugging. The controller interface is an Avalon-MM slave that also allows access to
the sink’s internal status registers.
The sink asserts the
rx_mgmt_irq
port when issuing an interrupt to the controller.
Related Information
DisplayPort Sink Register Map and DPCD Locations on page 10-1
AUX Interface
The IP core has three ports to control the serial data across the AUX channel:
• Data input (
rx_aux_in
)
• Data output (
rx_aux_out
)
• Output enable (
rx_aux_oe
). The output enable port controls the direction of data across the bidirec‐
tional link.
The AUX channel’s physical layer is a bidirectional 2.5 V SSTL Class II interface.
A state machine decodes the incoming AUX channel’s Manchester encoded data using the 16 MHz clock.
The message parsing drives the state machine input directly. The state machine performs all lane training
and EDID link-layer services.
The sink’s AUX interface also generates appropriate HPD IRQ events. These events occur if the sink’s
main link decoder detects a signal loss.
The sink core uses the
rx_cable_detect
signal to detect when a source (upstream) device is physically
connected and the
rx_pwr_detect
signal to detect when a source device is powered. These signals are
only used with MST mode. You should tie the signals to VCC when the sink is not in MST mode. The
sink core keeps the
rx_hpd
signal deasserted if both the
rx_cable_detect
and
rx_pwr_detect
signals are
not asserted.
AUX Debug Interface
The AUX controller lets you capture all bytes sent from and received by the AUX channel, which is useful
for debugging. The IP core supports a standard stream interface that can drive an Avalon-ST FIFO
component directly.
Table 5-10: Sink AUX Debug Interface Ports
The table below describes the stream ports.
Port Comments
rx_aux_debug_data[31:0] The sink AUX debug interface inserts a 1 µs timestamp counter in bits
[31:8]. Bits [7:0] represent the bytes received or transmitted.
rx_aux_debug_valid Qualifies valid stream data.
rx_aux_debug_sop Indicates the message packet’s first byte.
UG-01131
2015.05.04
Controller Interface 5-13
DisplayPort Sink Altera Corporation
Send Feedback