Altera DisplayPort MegaCore Function User Manual
Page 153
Table 10-2: DPRX_RX_CONTROL Bits
Bit
Bit Name
Function
31:30
Unused
29
LQA_ACTIVE
• 0 = Link Quality Analysis not used
• 1 = Link Quality Analysis in progress
28:24
Unused
23:16
RX_LINK_RATE
Main link rate expressed as multiples of 270 Mbps:
• 0×06 = 1.62 Gbps
• 0×0a = 2.7 Gbps
• 0×14 = 5.4 Gbps
15:14
Unused
13
RECONFIG_LINKRATE
This flag always reads back at 0.
1 = Reconfigure the transceiver with link rate
RX_LINK_
RATE
12:11
Unused
10
GXB_RESET
0 = Sink transceiver enabled
1 = Sink transceiver reset
9:8
TP
Current training pattern:
• 00 = Normal video
• 01 = Training pattern 1
• 10 = Training pattern 2
7
SCRAMBLER_DISABLE
0 = Scrambler enabled
1 = Scrambler disabled
6:5
Unused
4:0
LANE_COUNT
Lane count:
• 00001 = 1
• 00010 = 2
• 00100 = 4
This register is also available in read-only mode when not using a controller.
10-2
DPRX_RX_CONTROL
UG-01131
2015.05.04
Altera Corporation
DisplayPort Sink Register Map and DPCD Locations