Altera DisplayPort MegaCore Function - Manual (Page 90)

Figure 7-1: Simulation Example Block Diagram for Arria 10 Devices
DisplayPort IP Core
(a10_dp.qsys)
Native PHY IP Core
(gxb_tx.qsys)
Transceiver PHY Reset
Controller IP Core
(gxb_tx_reset.qsys)
Arria 10 Transceiver
ATX PLL IP Core
(gxb_tx_axt_pll.qsys)
Native PHY IP Core
(gxb_rx.qsys)
Reconfiguration
Management
Design Under Test
(a10_dp_example.v)
VGA
tx_mgmt
tx_video_in
rx_video_out tx_aux
rx_aux
tx_serial_data
rx_serial_data
clk16 clk100 clk135 tx_vid_clk rx_vid_clk
7-2 DisplayPort IP Core Simulation Example
UG-01131
2015.05.04
Altera Corporation DisplayPort IP Core Simulation Example
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