Altera DisplayPort MegaCore Function - Manual (Page 36)

Figure 4-10: Source Clock Tree
Front-End
Audio FIFO
Audio
Encoder
Secondary
Stream
Encoder
Front-End
Video FIFO
AUX
Controller
Controller
Interface
Sync
Back-End
Encoder
Sync
Sync
Sync
HSSIO0
HSSIO1
HSSIO2
HSSIO3
CMU PLL
tx_ss_clk
clk
txN_vid_clk
aux_clk
txN_audio_clk
Legend
Recovered Clock
from Transceiver
(tx_ss_clk)
Audio Clock
(txN_audio_clk)
Pixel Clock
(txN_vid_clk)
Secondary
Stream Data
Video Data
clk
aux_clk
DisplayPort Encoder Transceiver Block
270/135/81/67.5/40.5 MHz
Main
Link 0
Main
Link 1
Main
Link 2
Main
Link 3
Transceiver Reference Clock Signal(s) from PLL or Dedicated Pin } 135 MHz
Audio Data
4-20 Source Clock Tree
UG-01131
2015.05.04
Altera Corporation DisplayPort Source
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