Altera DisplayPort MegaCore Function - Manual (Page 70)

Interface Port Type Clock Domain Port Direction Description
Video Input Conduit
vidin_clk
vidin_clk Input Pixel clock.
vidin_data
(BPP*PIXEL
S_PER_
CLOCK–1:0)
Input Pixel data.
vidin_valid Input You must assert this
signal when all signals on
this port are valid.
vidin_sol Input Start of video line.
vidin_eol Input End of video line.
vidin_sof Input Start of video frame.
vidin_eof Input End of video frame.
vidin_
locked
Input You must assert this
signal when the Display‐
Port RX is locked to a
valid received video
stream.
• 1 = Video locked
• 0 = Video unlocked
UG-01131
2015.05.04
Clock Recovery Interface 6-9
DisplayPort IP Core Hardware Demonstration Altera Corporation
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