Altera DisplayPort MegaCore Function - Manual (Page 99)

Figure 7-6: RX Video Waveform
This timing diagram shows an example RX video waveform when interfacing to CVI. The
rx_vid_eol
signal generates the
h_sync
pulse by delaying it (by 1 clock cycle) to appear in the horizontal blanking
period after the active video ends (VALID is deasserted). The
rx_vid_eof
signal generates the
v_sync
pulse by delaying it (by 1 clock cycle) to appear in the vertical blanking period after the active video
ends (VALID is deasserted).
rx_vid_clk
rx_vid_valid
rx_vid_sol
rx_vid_eol
rx_vid_sof
ex_vid_eof
rx_vid_data
rx_cvi_datavalid
rx_cvi_f
rx_cvi_h_sync
rx_cvi_v_sync
rx_cvi_locked
rx_cvi_de
rx_cvi_data
Arria 10 Finite-State Machine (FSM)
The flow charts show the FSM flow for Arria 10 transceivers.
UG-01131
2015.05.04
Arria 10 Finite-State Machine (FSM) 7-11
DisplayPort IP Core Simulation Example Altera Corporation
Send Feedback