Altera DisplayPort MegaCore Function User Manual
Page 92
Table 7-1: Simulation Example Files for Arria 10 Devices
File Type
File
Description
System Verilog
HDL design
files
a10_dp_harness.sv
Top-level test harness.
Verilog HDL
design files
a10_dp_example.v
Design under test (DUT).
dp_analog_mappings.v
Table translating VOD and pre-emphasis settings.
a10_dp_reconfig_mgmt.v
Reconfiguration manager top-level.
a10_dp_rx_reconfig_mgmt.v
Reconfiguration manager FSM for an RX.
a10_dp_txpll_reconfig_mgmt.v
Reconfiguration manager FSM for a TX.
a10_dp_tx_reconfig_mgmt.v
Reconfiguration manager FSM for a TX analog.
clk_gen.v
Clock generation file.
freq_check.sv
Top-level file for the frequency checker.
rx_freq_check.sv
RX frequency checker.
tx_freq_check.sv
TX frequency checker.
vga_driver.v
VGA driver (generates a test image).
IP Catalog files
a10_dp.qsys
IP Catalog variant for the DisplayPort IP Core.
gxb_rx.qsys
IP Catalog variant for the RX transceiver.
gxb_tx.qsys
IP Catalog variant for the TX transceiver.
gxb_tx_atx_pll.qsys
IP Catalog variant for the Transceiver ATX PLL.
gxb_tx_reset.qsys
IP Catalog variant for the PHY Reset Controller.
Scripts
runall.sh
This script generates the IP simulation files and scripts,
and compiles and simulates them.
msim_dp.tcl
Compiles and simulates the design in the ModelSim
software.
7-4
Copy the Simulation Files to Your Working Directory
UG-01131
2015.05.04
Altera Corporation
DisplayPort IP Core Simulation Example