Altera DisplayPort MegaCore Function - Manual (Page 143)

DPTX_AUX_BYTE0
AUX Transaction Byte 0 Register.
Address: 0×0102
Direction: RW
Reset: 0×00000000
Table 9-41: DPTX_AUX_BYTE0 Bits
Bit Bit Name Function
31:8 Unused
7:0 BYTE Transaction address [15:8] for the next request, or
data(0) received in the last reply
DPTX_AUX_BYTE1
AUX Transaction Byte 1 Register.
Address: 0×0103
Direction: RW
Reset: 0×00000000
Table 9-42: DPTX_AUX_BYTE1 Bits
Bit Bit Name Function
31:8 Unused
7:0 BYTE Transaction address [7:1] for the next request, or data(1)
received in the last reply
DPTX_AUX_BYTE2
AUX Transaction Byte 2 Register.
Address: 0×0104
Direction: RW
Reset: 0×00000000
Table 9-43: DPTX_AUX_BYTE2 Bits
Bit Bit Name Function
31:8 Unused
9-22 DPTX_AUX_BYTE0
UG-01131
2015.05.04
Altera Corporation DisplayPort Source Register Map and DPCD Locations
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