Zilog Z16C35 - Manual (Page 102)

ISCC
User Manual
UM011002-0808
96
Bit 7, 6, and 5 are not used in the ISCC. These bits were used in the SCC cell to control the
action of the /WAIT//REQUEST pin but they have no function in the ISCC since this pin
does not exist in this device. For code compatibility purposes, there is no restriction on
how these bits are programmed.
Bit 4 and 3 specify the various character-available conditions that may cause interrupt
requests.
Bit combination 00 programs Receive Interrupts Disabled. This mode prevents the
receiver from requesting an interrupt and is normally used in a polled environment where
either the status bits in RR0 or the modified vector in RR2 (Channel B) can be monitored
to initiate a service routine. Although the receiver interrupts are disabled, a special condi-
tion can still provide a unique vector status in RR2.
Bit combination 01 programs Receive Interrupt on First Character or Special Condition.
The receiver requests an interrupt in this mode on the first available character (or stored
FIFO character) or on a special condition. Sync characters to be stripped from the message
stream do not cause interrupts.
Special receive conditions are: receiver overrun, framing error, end of frame, or parity
error (if selected). If a special receive condition occurs, the data containing the error is
stored in the receive FIFO until an Error Reset command is issued by the CPU.
This mode is usually selected when a Block Transfer mode is used. In this interrupt mode,
a pending special receive condition remains set until either an Error Reset Command, a
channel or hardware reset, or until receive interrupts are disabled.
The Receive Interrupt on First Character or Special Condition mode can be re-enabled by
the Enable Rx Interrupt on Next Character command in WR0.
Bit combination 10 programs Interrupt on All Receive Characters or Special Condition.
This mode allows an interrupt for every character received (or character in the receive
FIFO) and provides a unique vector when a special condition exists. The Receiver Over-
run bit and the Parity Error bit in RR1 are two special conditions that are latched. These
two bits must be reset by the Error Reset command. Receiver overrun is always a special
receive condition, and parity can be programmed to be a special condition.
Data characters with special receive conditions are not held in the receive FIFO in the
Interrupt On All Receive Characters or Special Conditions Mode as they are in the other
receive interrupt modes.
Bit combination 11 programs Receive Interrupt on Special Condition. This mode allows
the receiver to interrupt only on characters with a special receive condition. When an
interrupt occurs, the data containing the error is held in the receive FIFO until an Error
Reset command is issued. When using this mode in conjunction with a DMA, the DMA
can be initialized and enabled before any characters have been received by the SCC. This
eliminates the time-critical section of code required in the Receive Interrupt on First Char-
acter or Special Condition mode; i.e. all data can be transferred via the DMA so that the
CPU need not handle the first received character as a special case.
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