Zilog Z16C35 - Manual (Page 122)

ISCC
User Manual
UM011002-0808
116
5.4.15 Write Register 14 (Miscellaneous Control Bits)
WR14 contains some miscellaneous control bits. Bit positions for WR14 are shown in
Figure 5-16.
Figure 5–45. Write Register 14
Bit D7 and D5 are the Digital Phase-Locked Loop Command Bits
These three bits encode the eight commands for the Digital Phase-Locked Loop. A chan-
nel or hardware reset disables the DPLL, resets the missing clock latches, sets the source
to the /RTxC pin and selects NRZI mode. The Enter Search Mode command enables the
DPLL after a reset.
Bit combination 000 is the Null Command. This command has no effect on the DPLL.
Bit combination 001 is the Enter Search Mode Command. Issuing this command causes
the DPLL to enter the Search mode, where the DPLL searches for a locking edge in the
incoming data stream. The action taken by the DPLL upon receipt of this command
depends on the operating mode of the DPLL.
In NRZI mode, the output of the DPLL is High while the DPLL is waiting for an edge in
the incoming data stream. After the Search mode is entered, the first edge the DPLL sees
is assumed to be a valid data edge, and the DPLL begins the clock recovery operation
from that point. The DPLL clock rate must be 32x the data rate in NRZI mode. Upon leav-
ing the Search mode, the first sampling edge of the DPLL occurs 16 of these 32x clocks
after the first data edge and the second sampling occurs 48 of these 32x clocks after the
Null Command
Enter Search Mode
Reset Missing Clock
Disable DPLL
Set Source = BR Generator
Set Source = /RTxC
Set FM Mode
Set NRZI Mode
Write Register 14
D6 D7 D5 D4 D3 D2 D1 D0
BR Generator Enable
BR Generator Source
/DTR/Request Function
Auto Echo
Local Loopback
0
0
1
1
0
0
1
1 0
1
0
1
0
1
0
1 0
0
0
0
1
1
1
1
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