Zilog Z16C35 - Manual (Page 129)

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UM011002-0808
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External/Status conditions for changes. If none changed, Zero Count was the source. In
polled applications, check the IP bit in RR3A for a status change and then proceed as in
the interrupt service routine.
Bit 0 is Receive Character Available
This bit is set to “1” when at least one character is available in the receive FIFO and is
reset when the receive FIFO is completely empty. A channel or hardware reset empties the
receive FIFO.
5.5.2 Read Register 1
RR1 contains the Special Receive Condition status bits and the residue codes for the l-
field in SDLC mode. Figure 5-19 shows the bit positions for RR1.
Figure 5–48. Read Register 1
Bit 7 is the End of Frame (SDLC) status
This bit is used only in SDLC mode and indicates that a valid closing flag has been
received and that the CRC Error bit and residue codes are valid. This bit can be reset by
issuing the Error Reset command. It is also updated by the first character of the following
frame. This bit is reset in any mode other than SDLC.
Bit 6 is the CRC/Framing Error status
If a framing error occurs (in Asynchronous mode), this bit is set (and not latched) for the
receive character in which the framing error occurred. Detection of a framing error adds
an additional one-half bit to the character time so that the framing error is not interpreted
as a new Start bit. In Synchronous and SDLC modes, this bit indicates the result of com-
paring the CRC checker to the appropriate check value. This bit is reset by issuing an
Error Reset command, but the bit is never latched. Therefore, it is always updated when
Read Register 0
D6 D7 D5 D4 D3 D2 D1 D0
Rx Character Available
Zero Count
Tx Buffer Empty
DCD
Sync/Hunt
CTS
Tx Underrun/EOM
Break/Abort
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