Zilog Z16C35 - Manual (Page 142)

ISCC
User Manual
UM011002-0808
136
Bit 4 is Reserved. (This bit should be programmed as a zero to avoid conflicts with future
versions of this device.)
Bits 3 through 0 select the channel to which the command is to apply. More than one of
these bits may be set for the command; the command is applied to all of the DMA chan-
nels whose bits are set in this field: (These bits are not stored and must be written with
each command.)
Bit 3, when set, applies the command to the Receive A DMA.
Bit 2, when set, applies the command to the Transmit A DMA.
Bit 1, when set, applies the command to the Receive B DMA.
Bit 0, when set, applies the command to the Transmit B DMA.
5.6.6 Interrupt Status Register
This is a read only register which shares its address with the Interrupt Command Register.
The bits in this register reflect the status of the Interrupt Pending (IP) and Interrupt Under
Service (IUS) bits in the DMA channels. The bit positions for this register are shown in
Figure 5-31.
Bit 7 reflects the Receive A DMA Interrupt Under Service status. This bit can be set or
cleared through a command (see Interrupt Command Register). This bit is set to 1 auto-
matically during an interrupt acknowledge if this is the highest priority interrupt pending.
This is the highest priority pending interrupt if the corresponding Interrupt Pending bit is
set to 1, if the Interrupt Enable bit for this interrupt is set to 1, if the IEI input to the ISCC
is 1, if the DMA cell Master Interrupt Enable bit is set to 1, if there are no SCC cell inter-
rupts pending, and if there is no other DMA channel with an interrupt pending that is at a
higher priority level (see DMA Control Register for priority programming).
Figure 5–60. Interrupt Status Register
Address: 00011 (Read)
D6 D7 D5 D4 D3 D2 D1 D0
Tx B DMA IP
Rx B DMA IP
Tx A DMA IP
Rx A DMA IP
Tx B DMA IUS
Rx B DMA IUS
Tx A DMA IUS
Rx A DMA IUS
Page 136 of 316