Zilog Z16C35 - Manual (Page 191)

Application Note
The Z180™ Interfaced with the SCC at MHZ
7 -14
INPUT/OUTPUT CYCLES
Although the SCC is a universal design, certain timing
parameters differ from the Z180 timing. The following
subsections discuss the I/O interface for the Z180 MPU
and SCC. Z180 MPU to SCC Interface
Table 7 shows key parameters of the 10 MHz SCC for I/O
read/write cycles.
SCC I/O Read/Write Cycle
Assume that the Z180 MPU’s /IOC bit in the OMCR
(Operation Mode Control Register) clears to 0 (this
condition is a Z80 compatible timing mode for /IORQ and
/RD). The following are several design points to consider
(also see Table 3).
I/O Read Cycle
Parameters 8 and 9 mean that Address is stable 20 ns
before the falling edge of /RD and until /RD goes inactive.
Parameters 19 and 20 mean that /CE is stable at the falling
edge of /RD and until /RD goes inactive.
Parameter 22 means the /RD pulse width is wider than
125 ns.
Parameters 25 and 27 mean that Read data is available on
the data bus 120 ns later than the falling edge of /RD and
180 ns from a stable Address.
I/O Write Cycle
Parameters 6 and 7 mean that Address is stable 50 ns
before the falling edge of /WR and is stable until /WR goes
inactive.
Parameters 16 and 17 mean that /CE is stable at the falling
edge of /WR and is stable until /W goes inactive.
Parameter 28 means /WR pulse width is wider than 125
ns.
Parameters 28 and 29 mean that Write data is on the data
bus 10 ns before the falling edge of /WR. It is stable until
the rising edge of /WR.
Tables 8 and 9 show the worst case SCC parameters
calculating Z180 parameters at 10 MHz.
Table 7. 10 MHz SCC Timing Parameters for I/O Read/Write Cycle (Worst Case)
No Symbol Parameter Min Max Units
6 TsA(WR) Address to /WR Low Setup 50 ns
7 ThA(WR) Address to /WR High Hold 0 ns
8 TsA(RD) Address to /RD Low Setup 50 ns
9 ThA(RD) Address to /RD High Hold 0 ns
16 TsCEI(WR) /CE Low to /WR Low Setup 0 ns
17 ThCE(WR) /CE to /WR High Hold 0 ns
19 TsCEI(RD) /CE Low to /RD Low Setup 0 ns
20 ThCE(RD) /CE to /RD High Hold 0 ns
22 TwRDI /RD Low Width 125 ns
25 TdRDf(DR) /RD Low to Read Data Valid 120 ns
27 TdA(DR) Address to Read Data Valid 180 ns
28 TwWRI /WR Low Width 125 ns
29 TsDW(WR) Write Data to /WR Low Setup 10 ns
30 TdWR(W) Write Data to /WR High Hold 0 ns
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