Chapter 5 register descriptions, 1 introduction, 2 register descriptions – Zilog Z16C35 User Manual
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Chapter 5 Register Descriptions
5.1 INTRODUCTION
This section describes the function of the various bits in the registers of the device.
Throughout this section the following conventions will be used:
Control bits may be written and read by the CPU and will not be modified by the device.
Command bits may be written by the CPU to initiate an action in the device and will be
read as zeros. Status bits are controlled by the device and may be read to check device sta-
tus. Any writes to status bits are ignored by the device. Command/status bits are controlled
by both the device and the CPU. They may be written and read by the CPU and may also
be modified by the device.
Reserved bits are not used in this implementation of the device and may or may not be
physically present in the device. Reserved bits that are physically present will be readable
and writable but reserved bits that are not present will always be read as zero. To ensure
compatibility with future versions of the device reserved bits should always be written
with zeros. Reserved commands should not be used for the same reason.
5.2 REGISTER DESCRIPTIONS
Register can be accessed through either channel, the Interrupt Vector Read Register
returns the interrupt vector with status if read from Channel B and without status if read
from Channel A, and Channel A has an additional read register which contains all the
Interrupt Pending bits.
5.2.1 Write Registers, SCC Cell
Ten write registers are used for control, two for sync character generation, and two for
baud rate generation. In addition, there are two write registers which are shared by both
channels; one is the interrupt vector register, and one is the master interrupt control and
reset register. See Table 5-1 for a summary on write registers.
Table 5–23. SCC Cell Write Registers
Register
Description
WR0
Register Pointers, various initialization commands
WR1
Transmit and Receive interrupt enables, commands WAIT/DMA
WR2
Interrupt Vector
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