Zilog Z16C35 - Manual (Page 137)

ISCC
User Manual
UM011002-0808
131
Bit combination 110 is the command to enable the Transmitter A channel DMA. The
DMA operation is not triggered by this command.
Bit combination 111 is the command to enable the Receiver B channel DMA. The DMA
operation is not triggered by this command.
Bits 4 through 0 comprise the pointer to the internal registers. This pointer is used in the
non-multiplexed bus modes to access the DMA cell internal registers. After reset, the
internal pointer points to the Channel Command/Address Register. Access to other regis-
ters is accomplished by first writing the address of the desired register to this field. The
next access to the DMA cell will be to the register so addressed; this access may be a read
or a write. After this second access (the access to the desired register), the internal pointer
latch is cleared and the pointer again points to the Channel Command/Address Register.
5.6.2 DMA Status Register
This register is a read only register and is at the same address as the Channel Command/
Address Register. The individual bits indicate abort and terminal count of each of the four
DMA channels. Figure 5-27 shows the bit positions for the DMA Status Register. The sta-
tus in this register is automatically cleared after a read.
Figure 5–56. DMA Status Register
Bit 7, when set, indicates that the Receiver A DMA has reached terminal count.
Bit 6, when set, indicates that the Transmitter A DMA has reached terminal count.
Bit 5, when set, indicates that the Receiver B DMA has reached terminal count.
Bit 4, when set, indicates that the Transmitter B DMA has reached terminal count.
Bit 3, when set, indicates that the Receiver A DMA operation has been aborted.
Address: 00000 (Read)
D6 D7 D5 D4 D3 D2 D1 D0
Tx B DMA Abort
Rx B DMA Abort
Tx A DMA Abort
Rx A DMA Abort
Tx B DMA Terminal Count
Rx B DMA Terminal Count
Tx A DMA Terminal Count
Rx A DMA Terminal Count
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