Zilog Z16C35 - Manual (Page 322)

Z16C35 ISCC™ User’s Manual
Zilog ISCC ™ Controller
18-2
ISCC QUESTIONS AND ANSWERS (Continued)
Q. What’s the recovery time required for the ISCC?
A. A recovery time may apply to ANY access of the ISCC.
Thus, a bus transaction before or after an access of
the ISCC looks like it requires that the recovery time be
met for those accesses. The timing for /Strobe signals,
i.e. /DS, /WR, /RD or Pulsed /INTACK relative to CLK
is three clocks if /Strobe, synched to the /INTACK rel-
ative to CLK, is three clocks if /Strobe is synched to the
rising edge of CLK; or four clocks otherwise. The Re-
covery time is independent of /CS. Please note, if in
any design application with the ISCC the reads and
writes are unreliable, this recovery timing should be
checked very carefully and as this could be a bug with
the ISCC.
Q: Is the SDLC FIFO available in ISCC?
A: Yes, the SDLC FIFO is available in the SCC cell of the
ISCC. There is a mistake in our ISCC Technical Man-
ual, P.5-20, on Register Description. The statement
'Bit 2 is not used and must be programmed “0”' is
wrong. Bit 2 of WR15 is used for enabling the SDLC
FIFO.
Q: Will DMA be enabled by writing the Enable
Command in the Channel Command/Address Reg-
ister?
A: Yes, DMA operation is triggered by the command,
“Enable DMA” on Channel Command/Address Regis-
ter. This is another mistake in our ISCC Technical
Manual, P.5-25, on Registe Description. The state-
ment “DMA operation is not triggered by this com-
mand” is wrong, e.g., Writing “100” to bits 7 through 5
enables and triggers TxB DMA operation.
Q: Will DMA operation be triggered by the DMA en-
able command in the DMA Enable Register?
A: Yes, DMA operation will also be triggered by setting
corresponding DMA Enable bits in the DMA Enable
Register (P.5-29 sec 5.6.7, DMA Enable Register in
ISCC Technical Manual). Note that this is a read/write
register. Read-modify-write instructions should be
used in writing this register to avoid the register value
to be overwritten and cause accidental enabling/dis-
abling of the DMA operations.
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