Zilog Z16C35 - Manual (Page 107)

ISCC
User Manual
UM011002-0808
101
Bit 7 and 6 are the Clock Mode, Bits 1 And 0
These bits specify the multiplier between the clock and data rates. In synchronous modes,
the 1X mode is forced internally and these bits are ignored unless External Sync mode has
been selected.
Bit combination 00 selects the 1X Mode. The clock rate and data rate are the same. In
External Sync mode, this bit combination specifies that only the /SYNC pin can be used to
achieve character synchronization.
Bit combination 01 selects the 16X Mode. The clock rate is 16 times the data rate. In
External Sync mode, this bit combination specifies that only the /SYNC pin can be used to
achieve character synchronization.
Bit combination 10 selects the 32X Mode. The clock rate is 32 times the data rate. In
External Sync mode, this bit combination specifies that either the /SYNC pin or a match
with the character stored in WR7 will signal character synchronization. The sync character
can be either six or eight bits long as specified by the 6-bit/8-bit Sync bit in WR10.
Bit combination 11 selects the 64X Mode. The clock rate is 64 times the data rate. With
this bit combination in External Sync mode, both the receiver and transmitter are placed in
SDLC mode. The only variation from normal SDLC operation is that the /SYNC pin can
be used to start or stop the reception of a frame by forcing the receiver to act as though a
flag had been received.
Bits 5 and 4 are the SYNC Mode selection Bits 1 And 0
These two bits select the various options for character synchronization. They are ignored
unless synchronous modes are selected in the stop bits field of this register.
Bit combination 00 selects the Monosync mode. In this mode, the receiver achieves char-
acter synchronization by matching the character stored in WR7 with an identical character
in the received data stream. The transmitter uses the character stored in WR6 as a time fill.
The sync character can be either six or eight bits, depending on the state of the 6-bit/8-bit
Sync bit in WR10. if the Sync Character Load Inhibit bit is set, the receiver strips the con-
tents of WR6 from the data stream if received within character boundaries.
Bit combination 01 selects the Bisync mode. The concatenation of WR7 with WR6 is used
for receiver synchronization and as a time fill by the transmitter. The sync character can be
12 or 16 bits in the receiver, depending on the state of the 6-bit/8-bit Sync bit in WR10.
The transmitted character is always 16 bits.
Bit combination 10 selects the SDLC Mode. In this mode, SDLC is selected and requires a
Flag (01111110) to be written to WR7. The receiver address field should be written to
WR6. The SDLC CRC polynomial must also be selected (WR5) in SDLC mode.
Bit combination 11 selects the External Sync Mode. In this mode, the ISCC expects exter-
nal logic to signal character synchronization via the /SYNC pin. If the crystal oscillator
option is selected (in WR11), the internal /SYNC signal is forced to “0.” In this mode, the
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