Zilog Z16C35 - Manual (Page 145)

ISCC
User Manual
UM011002-0808
139
requests pending, thus multiple channels may make DMA transfers without separate,
intervening bus acquisitions.
Bit 6 is reserved and should be programmed zero.
Bits 5 and 4 control the DMA priority according to Table 5-15. If DMA requests arise
simultaneously, the channel which is serviced first is the one with the highest priority as
programmed. Note that the interrupt priorities are not affected by this programming and
remain fixed in the order Rx A DMA (highest), Tx A DMA, Rx B DMA, Tx B DMA
(lowest).
Bit 3 selects if the DMA address for the Receive A DMA is to be incremented or decre-
mented after each DMA byte transfer. Programming this bit to a 1 causes the address to
increment; programming this bit to a 0 causes the address to decrement.
Bit 2 selects if the DMA address for the Transmit A DMA is to be incremented or decre-
mented after each DMA byte transfer. Its operation is identical to bit 3.
Bit 1 selects if the DMA address for the Receive B DMA is to be incremented or decre-
mented after each DMA byte transfer. Its operation is identical to bit 3.
Bit 0 selects if the DMA address for the Transmit B DMA is to be incremented or decre-
mented after each DMA byte transfer. Its operation is identical to bit 3.
5.6.9 Receive DMA Count Registers A, B
There are two sets of Receive DMA Count Registers, one set for Receive DMA Channel
A and one set for Receive DMA Channel B. Each register set contains two registers, one
for the low byte (bits 7-0) and one for the high byte (bits 15 - 8) as shown in Figure 5-34.
These registers are read/write.
Table 5–37. DMA Priority
D5 D4 DMA Priority
0 0 Rx A/Tx A/Rx B/Tx B
0 1 Rx B/Tx B/Rx A/Tx A
1 0 Rx A/Rx B/Tx A/Tx B
1 1 Rx B/Rx A/Tx B/Tx A
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