Zilog Z16C35 User Manual
Page 280
Application Note
Boost Your System Performance Using The Zilog ESCC
™
13-13
1
MODIFIED WRITE TIMING
In the SCC write cycle, the SCC assumes the data is valid
when /WR is asserted (Figure 15). This assumption is not
valid for some CPUs, e.g., the Intel 80X86. The /WR signal
from this CPU needs to delay for one more clock to initiate
the write cycle. Additional hardware is required.
In the ESCC, write cycle timing has been modified so that
data becomes valid a short time after write (approx. 20 ns).
Therefore, if the data pins from the Intel CPU are
connected directly to the ESCC, no additional logic is
required.
Figure 15. Modified Write Timing
/WR
SCC
ESCC
Databus Valid
Databus Valid
SCC Spec:
WR Falling
Databus Va
Minimum
ESCC Spec:
Databus Valid to WR Falling
Databus latched after falling edge of WR saves external logic required
to delay WR until databus is valid. Typically needed with Intel CPUs.
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