Zilog Z16C35 - Manual (Page 126)

ISCC
User Manual
UM011002-0808
120
If this bit is set to “1,” an External/Status interrupt is generated whenever the counter in
the baud rate generator reaches “0.” This bit is set to “0” by a channel or hardware reset.
Bit 0 is not used and must be programmed “0.”
5.5 READ REGISTERS
The ISCC SCC cell contains seven read registers in each channel. In addition, there are
two registers which are shared by both channels. The status of these registers is continu-
ally changing and depends on the mode of communication, received and transmitted data,
and the manner in which this data is transferred to and from the CPU. The following
description details the bit assignments for each register.
5.5.1 Read Register 0 (Transmit/receive buffer Status and External
Status)
Read Register 0 contains the status of the receive and transmit buffers. RR0 also contains
the status bits for the six sources of External/Status interrupts. The bit configuration is
illustrated in Figure 5-18.
Figure 5–47. Read Register 0
Bit 7 is the Break/Abort status
In the Asynchronous mode, this bit is set when a Break sequence (null character plus
framing error) is detected in the receive data stream. This bit is reset when the sequence is
terminated, leaving a single null character in the receive FIFO. This character should be
read and discarded. In SDLC mode, this bit is set by the detection of an Abort sequence
Read Register 0
D6 D7 D5 D4 D3 D2 D1 D0
Rx Character Available
Zero Count
Tx Buffer Empty
DCD
Sync/Hunt
CTS
Tx Underrun/EOM
Break/Abort
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