Zilog Z16C35 - Manual (Page 103)

ISCC
User Manual
UM011002-0808
97
Bit 2 selects Parity Is Special Condition
If this bit is set to “1,” any received characters with parity not matching the sense pro-
grammed in WR4 give rise to a Special Receive Condition. If parity is disabled (WR4),
this bit is ignored. A special condition modifies the status of the interrupt vector stored in
WR2. During an interrupt acknowledge cycle, this vector can be placed on the data bus.
Bit 1 is the Transmitter Interrupt Enable
If this bit is set to “1,” the transmitter requests an interrupt whenever the transmit buffer
becomes empty.
Bit 0 is the External/Status Master Interrupt Enable
This bit is the master enable for External/Status interrupts including /DCD, /CTS, /SYNC
pins, break, abort, the beginning of CRC transmission when the Transmit/Under-run/EOM
latch is set, or when the counter in the baud rate generator reaches “0.” Write Register 15
contains the individual enable bits for each of these sources of External/Status interrupts.
This bit is reset by a channel or hardware reset.
5.4.3 Write Register 2 (Interrupt Vector)
WR2 is the interrupt vector register. Only one vector register exists in the SCC cell, but it
can be accessed through either channel. The interrupt vector can be modified by status
information. This is controlled by the Vector Includes Status (VIS) and the Status High/
Status Low bits in WR9. The bit positions for WR2 are shown in Figure 5-4. Note that the
DMA cell has its own interrupt vector register.
Figure 5–33. Write Register 2
Write Register 2
D6 D7 D5 D4 D3 D2 D1 D0
V0
V1
V2
V3
V4
V5
V6
V7
Interrupt
Vector
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