Zilog Z16C35 - Manual (Page 106)

ISCC
User Manual
UM011002-0808
100
If the 6-bit sync option is selected with this bit set to “1,” all sync characters except the
one immediately preceding the data are stripped from the message. If the 6-bit sync option
is selected while in the Bisync mode, this bit is ignored.
The address recognition logic of the receiver is modified in SDLC mode if this bit is set to
“1,” i.e. only the four most significant bits of WR6 must match the receiver address. This
procedure allows the ISCC to receive frames from up to 16 separate sources without pro-
gramming WR6 for each source (if each station address has the four most significant bits
in common). The address field in the frame is still eight bits long.
The bit is ignored in SDLC mode if Address Search mode has not been selected.
Bit 0 is the Receiver Enable
When this bit is set to “1,” receiver operation begins. This bit should be set only after all
other receiver parameters are established and the receiver is completely initialized. This
bit is reset by a channel or hardware reset command, and it disables the receiver.
5.4.5 Write Register 4 (Transmit/Receiver Miscellaneous Parameters
and Modes)
WR4 contains the control bits for both the receiver and the transmitter. These bits should
be set in the transmit and receiver initialization routine before issuing the contents of
WR1, WR3, WR6, and WR7. Bit positions for WR4 are shown in Figure 5-6.
Figure 5–35. Write Register 4
Parity Enable
Parity EVEN/ODD
Sync Modes Enable
1 Stop Bit/Character
1 1/2 Stop Bits/Character
2 Stop Bits/Character
8-Bit Sync Character
16-Bit Sync Character
SDLC Mode (01111110 Flag)
External Sync Mode
X1 Clock Mode
X16 Clock Mode
X32 Clock Mode
X64 Clock Mode
Write Register 4
D6 D7 D5 D4 D3 D2 D1 D0
0
0
1
1 0
1
0
1
0
0
1
1 0
1
0
1
0
0
1
1 0
1
0
1
Page 100 of 316