Zilog Z16C35 - Manual (Page 113)

ISCC
User Manual
UM011002-0808
107
Bit combination 01 is the Channel Reset B Command. Issuing this command causes a
channel reset to be performed on Channel B.
Bit combination 10 is the Channel Reset A Command. Issuing this command causes a
channel reset to be performed on Channel A.
Bit combination 11 is the Force Hardware Reset Command. The effects of this command
are identical to those of a hardware reset, except that the Shift Right/Shift Left bit is not
changed and the MIE, Status High/Status Low and DLC bits take the programmed values
that accompany this command.
Bit 5 is not used and must be programmed “0.”
Bit 4 is the Status High//Status Low control bit
This bit controls which vector bits the SCC cell will modify to indicate status. When set to
“1,” the SCC cell modifies bits V6, V5, and V4 according to Table 5-7. When set to “0,”
the SCC cell modifies bits V1, V2, and V3 according to Table 5-5. This bit controls status
in both the vector returned during an interrupt acknowledge cycle and the status in RR2B.
This bit is reset by a hardware reset.
Bit 3 is the Master Interrupt Enable
This bit is set to 1 to globally enable interrupts, and cleared to zero to disable interrupts.
Clearing this bit to zero forces the IEO pin to follow the state of the IEI pin unless there is
an IUS bit set in the SCC cell. No IUS bit can be set after the MIE bit is cleared to zero.
This bit is reset by a hardware reset.
Bit 2 is the Disable Lower Chain control bit
The Disable Lower Chain bit can be used by the CPU to control the interrupt daisy-chain.
Setting this bit to “1” forces the IEO pin Low, preventing lower priority devices on the
Table 5–29. Interrupt Vector Modifications
V3 V2 V1 Status High/Status Low =0
V4 V5 V6 Status High/Status Low =1
0 0 0 Ch B Transmit Buffer Empty
0 0 1 Ch B External/Status Change
0 1 0 Ch B Receive Char. Available
0 1 1 Ch B Special Receive Condition
1 0 0 Ch A Transmit Buffer Empty
1 0 1 Ch A External/Status Change
1 1 0 Ch A Receive Char. Available
1 1 1 Ch A Special Receive Condition
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