Zilog Z16C35 User Manual
Page 169
Application Note
Interfacing Z80
®
CPUs to the Z8500 Peripheral Family
6-15
6
INTERRUPT ACKNOWLEDGE CYCLES
The primary timing differences between the Z80 CPUs and
Z8500 peripherals occur in the Interrupt Acknowledge
cycle. The Z8500 timing parameters that are significant
during Interrupt Acknowledge cycles are listed in Table 16,
while the Z80 parameters are listed in Table 17. The
reference numbers in Tables 16 and 17 refer to Figures 10,
12 and 13.
If the CPU and the peripherals are running at different
speeds (as with the Z80H interface), the /INTACK signal
must be synchronized to the peripheral clock.
Synchronization is discussed in detail under Interrupt
Acknowledge for Z80H CPU to Z8500/8500A Peripherals.
During an Interrupt Acknowledge cycle, Z8500 peripherals
require both /INTACK and /RD to be active at certain
times. Since the Z80 CPUs do not issue either /INTACK or
/RD, external logic must generate these signals.
Generating these two signals is easily accomplished, but
the Z80 CPU must be placed into a Wait condition until the
peripheral interrupt vector is valid. If more peripherals are
added to the daisy chain, additional Wait states may be
necessary to give the daisy chain time to settle. Sufficient
time between /INTACK active and /RD active should be
allowed for the entire daisy chain to settle.
Since the Z8500 peripheral daisy chain does not use the
IP flag except during interrupt acknowledge, there is no
need for decoding the RETI instruction used by the Z80
peripherals. In each of the Z8500 peripherals, there are
commands that reset the individual IUS flags.
EXTERNAL INTERFACE LOGIC
The following sections discuss external interface logic
required during Interrupt Acknowledge cycles for each
interface type.
CPU/Peripheral Same Speed
Figure 9 shows the logic used to interface the Z80A CPU
to the Z8500 peripherals and the Z80B CPU to Z8500A
peripherals during an Interrupt Acknowledge cycle. The
primary component in this logic is the Shift register
(74LS164), which generates /INTACK, /READ, and /WAIT.
.
Table 15. Z8500 Timing Parameters Interrupt Acknowledge Cycles
4 MHz
6 MHz
Worst Case
Min
Max
Min
Max
Units
1.
TsIA(PC)
/INTACK Low to PCLK High Setup
100
100
ns
ThIA(PC)
/INTACK Low to PCLK High Hold
100
100
ns
2.
TdIAi(RD)
/INTACK Low to RD (Acknowledge) Low
350
250
ns
5.
TwRDA
/RD (Acknowledge) Width
350
250
ns
3.
TdRDA(DR)
/RD (Acknowledge) to Data Valid
250
180
ns
TsIEI(RDA)
IEI to /RD (Acknowledge) Setup
120
100
ns
ThIEI(RDA)
IEI to /RD (Acknowledge) Hold
100
70
ns
TdIEI(IE)
IEI to IEO Delay
150
100
ns
Table 16. Z80 CPU Timing Parameters Interrupt Acknowledge Cycles
4 MHz
6 MHz
8 MHz
Worst Case
Min
Max
Min
Max
Min
Max
Units
TdC(M1f)
Clock High to /M1 Low Delay
100
80
70
ns
TdM1f(IORQf)
/M1 Low to /IORQ Low Delay
575*
*345
275*
ns
4. TsD(Cr)
Data to Clock High Setup
35
30
25
ns
*Z80A: 2TcC + TwCh + TfC - 65
Z80B: 2 TcC + TwCh + TfC - 50
Z80H: 2TcC + TwCh + TfC - 45
Page 163 of 316
UM011002-0808