Zilog Z16C35 User Manual
Page 207
Application Note
The Z180™ Interfaced with the SCC at MHZ
7-30
(Continued)
initscc:
ld
hl,scctab
; initialize scc
init0:
ld
a,(hl)
cp
0ffh
ret
z
out
(scc_cont),a
inc
hl
ld
a,(hl)
out
(scc_cont),a
inc
hl
jr
init0
;initialize z180’s scc
;
initdma:
ld
hl,addrtab
;initialize DMA
ld
c,sar0l
ld
b,dstat - sar0l
otimr
ld
a,00001100b
;dmac0 - i/o to mem++
out0
(dmode),a
ld
a,01001000b
;1 mem wait, no i/o wait,
;should be EDGE for Tx DMA
;NOT level
;- because of DTR/REQ timing
ret
txend:
ld
a,00010100b
;isr for dma1 int-complete tx
out0
(dstat),a
;disable dma1
set
0,b
;set status
ei
ret
rxend:
ld
a,00100000b
;isr for dma0 int
out0
(dstat),a
;disable dma0
set
1,b
;set status
ei
ret
;initialization data table for scc
;table format - register number, then value for the register
;and ends with 0ffh - since scc doesn’t have
;register 0ffh...
scctab:
db
09h
;select WR9
if scc_a
db
10000000b
;reset ch a
else
db
01000000b
;Reset Ch B
endif
db
04h
;select WR4
db
00000100b
;async,x1,1stop,parity off
Table 14. Test Program – Z180/SCC DMA Transfer (Continued)
Page 201 of 316
UM011002-0808