Zilog Z16C35 - Manual (Page 188)

Application Note
The Z180™ Interfaced with the SCC at MHZ
7
Write Cycle Timing
Figure 11 illustrates the SCC Write cycle timing. All
register addresses and /INTACK are stable throughout the
cycle. The timing specification of the SCC requires that the /CE signal (and address) be stable when /RD is active.
Data is available to the SCC before the falling edge of /WR
and remains active until /WR goes inactive.
Figure 10. SCC Read Cycle Timing
Address
/INTACK
/CE
/RD
D7-D0 Data Valid
Address Valid
Figure 11. SCC Write Cycle Timing
Address
/INTACK
/CE
/WR
D7-D0 Data Valid
Address Valid
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