Zilog Z16C35 User Manual
Page 153
ISCC
User Manual
UM011002-0808
147
Bits D2 and D1 program the Interrupt acknowledge type according to Table 5-16.
The Status Acknowledge is compatible with the 68000 family of microprocessors and the
Double Pulse Acknowledge is compatible withe the 8086 family or microprocessors.
Bit D0 selects the Shift Right/Shift Left address decoding mode for the DMA cell only. A
1 in this bit selects the Shift Right mode. In this mode, when the ISCC is in the multi-
plexed bus mode, the addresses to the DMA cell registers is decoded from address data
lines AD4 through AD0. A 0 in this bit selects the Shift Left mode. In this mode, when the
ISCC is in the multiplexed bus mode, the addresses to the DMA cell registers is decoded
from address data lines AD5 through AD1.
Table 5–38. Interrupt Acknowledge Programming
D2
D1
Interrupt Acknowledge Type
0
0
Status Acknowledge
0
1
Pulsed Acknowledge
1
0
Reserved
1
1
Double Pulse Acknowledge
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