Zilog Z16C35 - Manual (Page 133)

ISCC
User Manual
UM011002-0808
127
5.5.5 Read Register 8
RR8 is the Receive Data register.
5.5.6 Read Register 10
RR10 contains some miscellaneous status bits. Unused bits are always “0”. Bit position
for RR10 are shown in Figure 5-22.
Figure 5–51. Read Register 10
Bit 7 is the One Clock Missing status
While operating in the FM mode, the DPLL sets this bit to “1” when it does not see a clock
edge on the incoming lines in the window where it expects one. This bit is latched until
reset by a Reset Missing Clock or Enter Search Mode command in WR14. In the NRZI
mode of operation and while the DPLL is disabled, this bit is always “0”.
Bit 6 is the Two Clocks Missing status
While operating in the FM mode, the DPLL sets this bit to “1” when it does not see a clock
edge in two successive tries. At the same time the DPLL enters the Search mode. This bit
is latched until reset by a Reset Missing Clock or Enter Search Mode command in WR14,
bit 5-7. In the NRZI mode of operation and while the DPLL is disabled, this bit is always
“0”.
Bit 4 is the Loop Sending status
This bit is set to “1” in SDLC Loop mode while the transmitter is in control of the Loop,
that is, while the ISCC is actively transmitting on the loop. This bit is reset at all other
times.
Read Register 10
D6 D7 D5 D4 D3 D2 D1 D0
0
On Loop
0
0
Loop Sending
0
Two Clocks Missing
One Clock Missing
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