Zilog Z16C35 - Manual (Page 117)

ISCC
User Manual
UM011002-0808
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transmitted after the transmit underrun. This bit should be set after the first byte of data is
sent to the ISCC and reset immediately after the last byte of data so that the frame will be
terminated properly with CRC and a flag. This bit is ignored in Loop mode, but the pro-
grammed value is active upon exiting Loop mode. This bit is reset by a channel or hard-
ware reset.
Bit 1 is the Loop Mode control bit
In SDLC mode, the initial set condition of this bit forces the ISCC to connect TxD to RxD
and to begin searching the incoming data stream so that it can go on loop. All bits perti-
nent to SDLC mode operation in other registers must be set before this mode is selected.
The transmitter and receiver should not be enabled until after this mode has been selected.
As soon as the Go Active On Poll bit is set and an EOP is received, the ISCC goes on-
loop. If this bit is reset after the ISCC goes on-loop, the ISCC waits for the next EOP to go
off-loop.
In synchronous modes, the ISCC uses this bit, along with Go Active On Poll bit, to syn-
chronize the transmitter to the receiver. The receiver should not be enabled until after this
mode is selected. The TxD pin is held marking when this mode is selected unless a break
condition is prorammed. The receiver waits for a sync character to be received and then
enables the transmitter on a character boundary. The break condition, if programmed, is
removed. this mode works properly with sync characters of 6, 8, or 16 bits. This bit is ign-
nored in Asynchronous mode and is reset by a channel or hardware reset.
Bit 0 is the 6-Bit//8-Bit SYNC select bit
This bit is used to select a special case of synchronous modes. If this bit is set to “1” in
Monosync mode, the receiver and transmitter sync characters are six bits long instead of
the usual eight. If this bit is set to "1" in Bisync mode, the received sync will be 12 bits and
the transmitter sync character will remain 16 bits long. This bit is ignored in SDLC and
Asynchronous modes, but still has effect in the special external sync modes. This bit is
reset by a channel or hardware reset.
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