Zilog Z16C35 - Manual (Page 124)

ISCC
User Manual
UM011002-0808
118
works with any Transmit/Receive mode except Loop mode. For meaningful results, the
frequency of the transmit and receive clocks must be the same. This bit is reset by a chan-
nel or hardware reset.
Bit 3 is the Auto Echo select bit
Setting this bit to “1” selects the Auto Echo mode of operation. In this mode, the TxD pin
is connected to RxD, as in Local Loopback mode, but the receiver still listens to the RxD
input. Transmitted data is never seen inside or outside the ISCC in this mode, and /CTS is
ignored as a transmit enable. This bit is reset by a channel or hardware reset.
Bit 2 is the DTR/Request Function select bit
This bit selects the function of the /DTR//REQ pin. If this is set to “0,” the /DTR//REQ pin
follows the state of the DTR bit in WR5. If this bit is set to “1,” the /DTR//REQ pin goes
Low whenever the transmit buffer becomes empty and in any of the synchronous modes
when CRC has been sent at the end of a message. The /DTR//REQ does not go inactive
until the internal operation satisfying the request is complete, which occurs three to four
PCLK cycles after the falling edge of /DS, /READ or /WRITE. This bit is reset by a chan-
nel or hardware reset. Note that the /REQUEST function of this pin is not related to the
operation of the ISCC DMA cell. Since a DMA function is present on this device, the /
REQUEST function would not normally be used.
Bit 1 is the Baud Rate Generator Source select bit
This bit selects the source of the clock for the baud rate generator. If this bit is set to “0.”
The baud rate generator clock comes from either the /RTxC pin or the XTAL oscillator
(depending on the state of the XTAL/NO XTAL bit). If this bit is set to “1,” the clock for
the baud rate generator is the ISCC’s PCLK input. Hardware reset sets this bit to “0,”
selecting the /RTxC pin as the clock source for the baud rate generator.
Bit 0 is the Baud Rate Generator Enable
This bit controls the operation of the baud rate generator. The counter in the baud rate gen-
erator is enabled for counting when this bit is set to “1,” and counting is inhibited when
this bit is set to “0.” When this bit is set to “1,” change in the state of this bit is not
reflected by the output of the baud rate generator for two counts of the counter. This
allows the command to be synchronized. However, when set to “0,” disabling is immedi-
ate. This bit is reset by a hardware reset.
5.4.16 Write Register 15 (External/Status Interrupt Control)
WR15 is the External/Status Source Control register. If the External/Status interrupts are
enabled as a group via WR1, bits in this register control which External/Status conditions
can cause an interrupt. Only the External/Status conditions that occur after the controlling
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