Zilog Z16C35 User Manual
Page 274
Application Note
Boost Your System Performance Using The Zilog ESCC
™
13-7
1
AUTOMATIC /RTS DEASSERTION
Several SDLC enhancements are provided in the ESCC.
The ESCC allows automatic /RTS deassertion at End Of
Frame (EOF). The automatic /RTS deassertion is enabled
by setting WR7' D2. If ESCC is programmed for SDLC
mode and the Flag-On-Underrun bit (WR10 D2) is reset,
with the RTS bit (WR5 D1) reset, /RTS is deasserted
automatically at the last bit of the closing flag. It is triggered
by the rising edge of the Transmit Clock (TxC - Figures 6
and 7).
/RTS is normally used in SDLC for switching the direction
of line drivers. Automatic /RTS deassertion allows optimal
line switching without any software intervention. The
typical procedures are as follows:
1.
Enable Automatic /RTS Deassertion
2.
Before frame transmission, set RTS bit
3.
Enable frame transmission
4.
Reset RTS bit
5.
RTS pin deassertion is delayed until the last rising TxC
edge closing flag.
Figure 6. /RTS Deassertion Timing
TX Underrun/EOM
/RTS Pin
Data
CRC1
CRC2
Flag
RTS Bit
(WR5, D1)
Data Being Sent
Figure 7. /RTS Deassertion Sequence
TX Closing
Flag
TXC
TXD
/RTS
Mark
Automatic RTS Pin Deactivation
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