Zilog Z16C35 - Manual (Page 99)

ISCC
User Manual
UM011002-0808
93
Bit combination 011 is the Send Abort Command
This command is used in SDLC mode to transmit a sequence of eight to thirteen “1s.” This
command always empties the transmit buffer and sets Tx Underrun/EOM bit in Read Reg-
ister 0.
Bit combination 100 is the Enable Interrupt On Next Rx Character Command
If the interrupt on First Received Character mode is selected, this command is used to
reactivate that mode after each message is received. The next character to enter the receive
FIFO causes a Receive interrupt. Alternatively, the first previously stored character in the
FIFO will cause a Receive interrupt.
Bit combination 101 is the Reset Tx Interrupt Pending Command
This command is used in cases where there are no more characters to be sent; e.g., at the
end of a message. This command prevents further transmit interrupts until after the next
character has been loaded into the transmit buffer or until CRC has been completely sent.
This command is necessary to prevent the transmitter from requesting an interrupt when
the transmit buffer becomes empty (with Transmit Interrupt Enabled).
Bit combination 110 is the Error Reset Command
This command resets the error bits in RR1. If interrupt on first Rx Character or interrupt
on Special Condition modes are selected and a special condition exists, the data with the
special condition is held in the receive FIFO until this command is issued. If either of
these modes is selected and this command is issued before the data has been read from the
receive FIFO, the data is lost.
Bit combination 111 is the Reset Highest IUS Command
This command resets the highest priority Interrupt Under Service (IUS) bit, allowing
lower priority conditions to request interrupts. This command allows the use of the inter-
nal daisy-chain (even in systems without an external daisy-chain) and should be the last
operation in an interrupt service routine.
Bits 2 through 0 are the Register Selection Code when the device is programmed to be in
the non-multiplexed bus mode. These three bits select Registers 0 through 7. With the
Point High command, Registers 8 through 15 are selected.
In the multiplexed bus mode, bits D2 through D0 have the following function.
Bit D2 must be programmed as “0.” Bits D1 and D0 select Shift Left/Right; that is
WR0(1-0)=10 for shift left and WR0(1-0)=11 for shift right.
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