Zilog Z16C35 - Manual (Page 118)

ISCC
User Manual
UM011002-0808
112
5.4.12 Write Register 11 (Clock Mode Control)
WR11 is the Clock Mode Control Register. The bits in this register control the sources of
both the receive and transmit clocks, the type of signal on the /SYNC and /RTxC pins, and
the direction of the /TRxC pin. Bit positions for WR11 are shown in Figure 5-13.
Figure 5–42. Write Register 11
Bit 7 is the RTxC-XTAL//NO XTAL select bit
This bit controls the type of input signal the ISCC expects to see on the /RTxC pin. If this
bit is set to “0,” the ISCC expects a TTL-compatible signal as an input to this pin. If this
bit is set to “1,” the ISCC connects a high-gain amplifier between the /RTxC and /SYNC
pins in expectation of a quartz crystal being placed across the pins.
The output of this oscillator is available for use as a clocking source. In this mode of oper-
ation, the /SYNC pin is unavailable for other use. The /SYNC signal is forced to “0” inter-
nally. A hardware reset forces /NO XTAL. (At least 20 ms should be allowed after this bit
is set to 1, to allow the oscillator to stabilize.)
Bits 6 and 5 are the Receiver Clock select bits 1 and 0
These bits determine the source of the receive clock as shown in Table 5-9. They do not
interfere with any of the modes of operation in the SCC cell, but simply control a multi-
/TRxC Out = Xtal Output
/TRxC Out = Transmit Clock
/TRxC Out = BR Generator Output
/TRxC Out = DPLL Output
Transmit Clock = /RTxC Pin
Transmit Clock = /TRxC Pin
Transmit Clock = BR Generator Output
Transmit Clock = DPLL Output
Receive Clock = /RTxC Pin
Receive Clock = /TRxC Pin
Receive Clock = BR Generator Output
Receive Clock = DPLL Output
Write Register 11
D6 D7 D5 D4 D3 D2 D1 D0
0
0
1
1 0
1
0
1
0
0
1
1 0
1
0
1
0
0
1
1 0
1
0
1
/RTxC Xtal/No Xtal
TRxC O/I
Page 112 of 316