Zilog Z16C35 - Manual (Page 116)

ISCC
User Manual
UM011002-0808
110
Bit 4 is the Go Active On Poll control bit
When Loop mode is first selected during SDLC operation, the ISCC connects RxD to TxD
with only gate delays in the path. The ISCC does not go on-loop and insert the 1-bit delay
between RxD and TxD until this bit has been set and an EOP received. When the ISCC is
on-loop, the transmitter can not go active unless this bit is set at the time an EOP is
received. The ISCC examines this bit whenever the transmitter is active in SDLC Loop
mode and is sending a flag. If this bit is set at the time the flag is leaving the Transmit Shift
register, another flag or data byte (if the transmit buffer is full) is transmitted. If the Go
Active on Poll bit is not set at this time, the transmitter finishes sending the flag and
reverts to the 1-Bit Delay mode. Thus, to transmit only one response frame, this bit should
be reset after the first data byte is sent to the ISCC, but before CRC has been transmitted.
If the bit is not reset before CRC is transmitted, extra flags are sent, slowing down
response time on the loop. If this bit is reset before the first data is written, the ISCC com-
pletes the transmission of the present flag and reverts to the 1-Bit Delay mode. After gain-
ing control of the loop, the ISCC is not able to transmit again until a flag and another EOP
have been received. Though not strictly necessary, it is good practice to set this bit only
upon receipt of a poll frame to ensure that the ISCC does not go on-loop without the CPU
noticing it.
In synchronous modes other than SDLC with the Loop Mode bit set, this bit must be set
before the transmitter can go active in response to a received sync character.
This bit is always ignored in Asynchronous mode and Synchronous modes unless the
Loop Mode bit is set. This bit is reset by a channel or hardware reset.
Bit 3 is the Mark//Flag Idle line control bit
This bit affects only SDLC operation and is used to control the idle line condition. If this
bit is set to “0,” the transmitter send flags as an idle line. If this bit is set to “1,” the trans-
mitter sends continuous “1s” after the closing flag of a frame. The idle line condition is
selected byte by byte; i.e., either a flag or eight “1s” are transmitted. The primary station in
an SDLC loop should be programmed for Mark Idle to create the EOP sequence. Mark
Idle must be deselected at the beginning of a frame before the first data is written to the
ISCC, so that an opening flag can be transmitted. This bit is ignored in Loop mode, but the
programmed value takes effect upon exiting the Loop mode. This bit is reset by a channel
or hardware reset.
Bit 2 is the Abort//Flag On Underrun select bit
This bit affects only SDLC operation and is used to control how the ISCC responds to a
transmit underrun condition. If this bit is set to “1” and a transmit underrun occurs, the
ISCC sends an abort and a flag instead of CRC. If this bit is reset, the ISCC sends CRC on
a transmit underrun. At the beginning of this 16-bit transmission, the Transmit Underrun/
EOM bit is set, causing an External/Status interrupt. The CPU uses this status, along with
the byte count from memory or the DMA, to determine whether the frame must be retrans-
mitted. A transmit buffer Empty interrupt occurs at the end of this 16-bit transmission to
start the next frame. If both this bit and the Mark/Flag Idle bit are set to “1,” all “1s” are
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