Zilog Z16C35 - Manual (Page 68)

ISCC
User Manual
UM011002-0808
62
The receiver in the ISCC searches for character synchronization only while it is in Hunt
mode. In this mode the receiver is idle having been first enabled, and may be placed in
Hunt mode by command from the processor. This is accomplished by issuing the Enter
Hunt Mode command in WR3. This bit (D4) is a command; writing a “0” to it has no
effect. The Hunt status of the receiver is reported by the Sync/Hunt is one of the possible
sources of external/status interrupts, with both transitions causing an interrupt. This is true
even if the Sync/Hunt bit is set as a result of the processor issuing the Enter Hunt Mode
command.
The number of bits per character is controlled by bits D7 and D6 of WR3. Five, six, seven,
or eight bits per character may be selected via these two bits. The data is right-justified in
the receive data buffer. The ISCC merely takes a snapshot of the receive data stream at the
appropriate times so the “unused” bits in the receive buffer are only the bits following the
character in the data stream.
An additional bit, carrying parity information, may be selected by setting bit D0 of WR4
to “1”. If this bit is set to “1”, the received character is checked for even parity, if set to
“0”, the received character is checked for odd parity. The additional bit per character is not
visible when there are eight data bits per character. The Parity Error bit in the receive error
FIFO may be programmed to cause a Special Receive Condition interrupt by setting bit
D2 of WR1 to “1”. This error bit is latched and so will remain active, once set, until an
Error Reset command has been issued. If interrupts are not used to transfer data the Parity
Error, CRC Error, and Overrun Error bits in RR1 should be checked before the data is
removed from the receive data FIFO.
The character length may be changed at any time before the new number of bits has been
assembled by the receiver, but, care should be exercised as unexpected results may occur.
A representative example, switching from five bits to eight bits and back to five bits is
shown in Figure 4-8.
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