Zilog Z16C35 - Manual (Page 311)

16-1
A
PPLICATION
N
OTE
I
NTERFACING THE
ISCC™
TO THE
68000
AND
8086
INTRODUCTION
The ISCC™ uses its flexible bus to interface with a variety
of microprocessors and microcontrollers; included are the
68000 and 8086.
The Z16C35 ISCC is a Superintegration form of the
85C30/80C30 Serial Communications Controller (SCC).
Super integration includes four DMA channels, one for
each receiver and transmitter and a flexible Bus Interface
Unit (BIU). The BIU supports a wide variety of buses
including the bus types of the 680X0 and the 8086 families
of microprocessors.
This Application Note presents the details of BIU operation
for both slave peripheral and DMA modes. Included are
application examples of interconnecting an ISCC to a
68000 and a 8086 (These examples are currently under
test).
ISCC BUS INTERFACE UNIT (BIU)
The following subsections describe and illustrate the
functions and parameters of the ISCC Bus Interface Unit.
Overview
The ISCC™ contains a flexible bus interface that is directly
compatible with a variety of microprocessors and
microcontrollers. The bus interface unit adds to the chip by
allowing ease of connection to several standard bus
configurations; among others are the 68000 and the 8086
family microprocessors. This compatibility is achieved by
initializing the ISCC after a reset to the desired bus
configuration.
The device also configures to work with a variety of other
8- or 16-bit bus systems and is used with address/data
multiplexed or non-multiplexed buses. In addition, the
wait/ready handshake, the interrupt acknowledge, and the
bus high byte/low byte selection are all programmable.
Separate read/write, data strobe, write, read, and address
strobe signals are available for direct system interface with
a minimum of external logic.
Modes Description
There are basically two bus modes of operation:
multiplexed and non-multiplexed. In the multiplexed bus
mode, the ISCC internal registers are directly accessible
as separate registers with their own unique hardware
addresses. By contrast, in the non-multiplexed mode, all
registers access through an internal pointer which first
loads with the register address. Loading of the pointer is
done as a data write. In either case, there are some
external addressing signals.
Chip Enable (CE) allows external selection through the
decode of upper order address bits like accessing
separate chips. A separate input (not part of the AD15-
AD0 bus connection) selects between the internal SCC
and DMA sections of the chip. This input is A0/SCC/DMA
and provides direct transfers to the appropriate chip
subsystem; either multiplexed or non-multiplexed bus
mode.
A second separate input (not part of the AD15-AD0 bus
connection) provides for a selection between the internal
SCC; both channels A and B (Table A-1). This input is
A1/A/B and provides direct transfers to the appropriate
SCC channel when A0/SCC/DMA selects the SCC; either
multiplexed or non-multiplexed bus mode. Note that these
two signals, A1/A/B and A0/SCC/DMA, are inputs when
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