Zilog Z16C35 - Manual (Page 233)

Application Note
SCC in Binary Synchronous Communications
10-3
9
Figure 2. Block Diagram of Z8000 DM
Address/
Data
Buffer
Wire Wrap Area
Reset
Switch
NMI
Switch
Reset
Non-maskable
Interrupt
Segment
Address
Buffer
Status
Decoder
I/O
Control
Eprom
Control
Ram
Control
Z80A PIO's
(2)
Z80A CTC SIO2
Eprom
Memory
(8k Words Max)
Dynamic
Ram Memory
(32k Words Max)
Serial
Output
Buffers
RS-232C
Serial
Channels
(2)
Address
Data
Segment
Address
Status
Control
Out
Clock
Buffer
Control
Inputs
External
Clock
In/Out
Clock
Generator
CONTROL
BUS
EPROM CONTROL BUS
RAM CONTROL BUS
I/O BUS
ADDRESS/DATA BUS
Figure 3. Block Diagram of Two Z8000 Development Modules
Z8002
Z-SCC
Z8002
Z-SCC
TxD
TRxC
RTxC
RxD
RxD
RTxC
TRxC
TxD
Local Remote
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