Zilog Z16C35 - Manual (Page 125)

ISCC
User Manual
UM011002-0808
119
bit are sent to “1” will cause an interrupt. This is true, even if an External/Status condition
is pending at the time the bit is set. Bit positions for WR15 are shown in Figure 5-17.
Figure 5–46. Write Register 15
Bit 7 is the Break/Abort Interrupt Enable
If this bit is set to “1,” a change in the Break/Abort status of the receiver causes an Exter-
nal/Status interrupt. This bit is set by a channel or hardware reset.
Bit 6 is the Transmit Underrun/EOM Interrupt Enable
If this bit is set to “1,” a change of state by the Tx Underrun/EOM latch in the transmitter
causes an External/Status interrupt. This bit is set to “1” by a channel or hardware reset.
Bit 5 is the CTS Interrupt Enable
If this bit is set to “1,” a change of state on the /CTS pin causes an External/Status Inter-
rupt. This bit is set by a channel or hardware reset.
Bit 4 is the SYNC/Hunt Interrupt Enable
If this bit is set to “1,” a change of state on the /SYNC pin causes an External/Status inter-
rupt in Asynchronous mode, and a change of state in the Hunt bit in the receiver causes
and External/Status interrupt in synchronous modes. This bit is set by a channel or hard-
ware reset.
Bit 3 is the DCD Interrupt Enable
If this bit is set to “1,” a change of state on the /DCD pin causes an External/Status inter-
rupt. This bit is set by a channel or hardware reset.
Bit 2 is not used and must be programmed “0.”
Bit 1 is the Zero Count Interrupt Enable
Write Register 15
D6 D7 D5 D4 D3 D2 D1 D0
0
Zero Count IE
SDLC FIFO Enable
DCD IE
Sync/Hunt IE
CTS IE
Tx Underrun/EOM IE
Break/Abort IE
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