Zilog Z16C35 - Manual (Page 114)

ISCC
User Manual
UM011002-0808
108
daisy-chain from requesting interrupts. This bit is reset by a hardware reset. (Note that in
the ISCC this will also prevent the DMA cell from requesting interrupts.)
Bit 1 is the No Vector select bit
The No Vector bit controls whether or not the ISCC will respond to an interrupt acknowl-
edge cycle by placing a vector on the data bus if the ISCC is the highest priority device
requesting an interrupt. If this bit is set, no vector is returned; i.e., AD7-AD0 remain three-
stated during an inter-rupt acknowledge cycle, even if the ISCC is the highest priority
device requesting an interrupt.
Bit 0 is the Vector Includes Status control bit
The Vector Includes Status Bit controls whether or not the SCC cell will include status
information in the vector it places on the bus in response to an interrupt acknowledge
cycle. If this bit is set, the vector returned is variable, with the variable field depending on
the highest priority IP that is set. Table 5-5 shows the encoding of the status information.
This bit is ignored if the No Vector (NV) bit is set.
5.4.11 Write Register 10 (Miscellaneous Transmitter/Receiver Control
Bits)
WR10 contains miscellaneous control bits for both the receiver and the transmitter. Bit
positions for WR10 are shown in Figure 5-11.
Figure 5–40. Write Register 10
Write Register 10
D6 D7 D5 D4 D3 D2 D1 D0
6 Bit/8 Bit Sync
Loop Mode
Abort/Flag On Underrun
Mark/Flag Idle
Go Active On Poll
CRC Preset I/O
NRZ
NRZI
FM1 (Transition = 1)
FM0 (Transition = 0) 0
0
1
1 0
1
0
1
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