Zilog Z16C35 - Manual (Page 112)

ISCC
User Manual
UM011002-0808
106
5.4.9 Write Register 8 (Transmit Buffer)
WR8 is the transmit buffer register.
5.4.10 Write Register 9 (Master Interrupt Control)
WR9 is the Master Interrupt Control register and contains the Reset command bits. Only
one WR9 exists in the ISCC and can be accessed from either channel. The Interrupt con-
trol bits can be programmed at the same time as the Reset command because these bits are
only reset by a hardware reset. Bit positions for WR9 are shown in Figure 5-10.
Figure 5–39. Write Register 9
Bit 7 and 6 are the Reset Command Bits
Together, these bits select one of the reset commands for the SCC cell. Setting either of
these bits to “1” disables both the receiver and the transmitter in the corresponding chan-
nel, forces TxD for that channel marking, forces the modem control signals High in that
channel, resets all IPs and IUSs and disables all interrupts in that channel. Four extra
PCLK cycles must be allowed beyond the usual cycle time after any of the active reset
commands is issued before any additional commands or controls are written to the channel
affected. In the non-multiplexed bus mode, four extra PCLK cycles must be allowed
beyond the usual cycle time before any additional command or controls are written to the
SCC cell.
Bit combination 00 is a Null Command. This command has no effect. It is used when a
write to WR9 is necessary for some reason other than an SCC cell Reset command.
Write Register 9
D6 D7 D5 D4 D3 D2 D1 D0
VIS
NV
DLC
MIE
Status High/Status L
0
0
0
1
1 0
1
0
1 No Reset
Channel Reset B
Channel Reset A
Force Hardware Reset
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