Zilog Z16C35 - Manual (Page 138)

ISCC
User Manual
UM011002-0808
132
Bit 2, when set, indicates that the Transmitter A DMA operation has been aborted.
Bit 1, when set, indicates that the Receiver B DMA operation has been aborted.
Bit 0, when set, indicates that the Transmitter B DMA operation has been aborted.
5.6.3 Interrupt Control Register
The Interrupt Control Register is used to enable the interrupts from the individual sources,
and select the interrupt vector options. This register is read/write. The bit positions are
shown in Figure 5-28.
Figure 5–57. Interrupt Control Register
Bit 7 is the Master Interrupt Enable (MIE). When this bit is cleared, all interrupts from the
DMA cell are disabled even though the individual enable bits are set. This bit must be set
for any DMA interrupt source to cause an interrupt.
Bit 6 is the disable lower chain control bit (DLC). If this bit is set, the external lower chain
of the daisy chained interrupt structure is disabled; IEO will not become active.
Bit 5 selects the no vector option. With this bit set, the DMA cell does not return an inter-
rupt vector to the CPU. During the interrupt acknowledge cycle when the interrupt vector
is requested, the ISCC will not drive the bus. With this bit clear, an interrupt vector will be
returned in the interrupt acknowledge cycle.
Bit 4 selects the vector include status option for the interrupt vector from the DMA cell.
With this bit clear, a DMA interrupt vector will be returned which is the vector that has
been programmed into the Interrupt Vector Register. With this bit set, the returned vector
contains status information concerning the interrupt source. The status returned reflects
the highest priority interrupt pending (IP bit is set and the corresponding Interrupt Enable
Address: 00001
D6 D7 D5 D4 D3 D2 D1 D0
Tx B DMA Interrupt Enable
Rx B DMA Interrupt Enable
Tx A DMA Interrupt Enable
Rx A DMA Interrupt Enable
VIS
NV
DLC
MIE
Page 132 of 316