Zilog Z16C35 - Manual (Page 7)

ISCC
User Manual
UM011002-0808
1
Chapter 1 General Description
1.1 INTRODUCTION
The Z16C35, ISCC is a CMOS superintegration device with a flexible Bus Interface Unit
(BIU) connecting a built-in Direct Memory Access (DMA) cell to the CMOS Serial Com-
munications Control (SCC) cell.
The ISCC is a dual-channel, multi-protocol data communications peripheral which easily
interfaces to CPU’s with either multiplexed or non-multiplexed address and data buses.
The advanced CMOS process offers lower power consumption, higher performance, and
superior noise immunity. The programming flexibility of the internal registers allow the
ISCC to be configured for a wide variety of serial communications applications. The many
on-chip features such as streamlined bus interface, four channel DMA, baud rate genera-
tors, digital phase-locked loops, and crystal oscillators dramatically reduce the need for
external logic. Additional features, including a 10x19 bit status FIFO, are added to support
high speed SDLC transfers using on-chip DMA controllers.
The ISCC can address up to 4 gigabytes per DMA channel by using the /UAS and /AS sig-
nals to strobe out 32-bit multiplexed addresses.
The ISCC handles asynchronous formats, synchronous byte-oriented protocols such as
IBM Bisync, and synchronous bit-oriented protocols such as HDLC and IBM SDLC. This
versatile device supports virtually any serial data transfer application (terminals, printers,
diskette, tape drives, etc.).
The device can generate and check CRC codes in any synchronous mode and can be pro-
grammed to check data integrity in various modes. The ISCC also has facilities for modem
controls in both channels. In applications where these controls are not needed, the modem
controls can be used for general-purpose I/O.
The standard Zilog interrupt daisy chain is supported for interrupt hierarchy control. Inter-
nally, the SCC cell has higher interrupt priority than the DMA cell.
The DMA cell consists of four DMA channels; one for transmit and one for receive to and
from each SCC channel, respectively.
The DMA cell adopts a simple fly-by-mode DMA transfer, providing a powerful and effi-
cient DMA access. The cell does not support memory-to-memory transfer.
Priorities between the four DMA channels are programmable to custom-fit user applica-
tions. Arbitration of Bus prior-ity control signals between the ISCC DMA and other sys-
tem DMA’s should be handled outside the ISCC.
The BIU has a universal interface to most system/CPU bus structures and timing. The first
write to the ISCC after a hardware reset will configure the bus interface type being imple-
mented.
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