Comtech EF Data CDD-562L - Manual (Page 27)

CDD-562L/564 Demodulator with IP Module Revision 2
Introduction MN/CDD564L.IOM
1–3
1.2 Functional Description
The CDD-562L has two Rx channels. The CDD-564/564L have four Rx channels.
The demodulators have two fundamentally different types of interface: Ethernet and IF.
The Ethernet interface is a bidirectional path, which connects with the customer’s equipment
through an Ethernet Switch. The Ethernet interface is a 10/100 BaseT Ethernet port where data
flow is the combined output of the demodulator channels. Control and status information also
uses this port.
The IF interfaces provides independent unidirectional links (Rx only) with the satellite via the
downlink equipment.
In the demodulator, the Rx IF signal in the range (50–90 or 100–180 MHz for 70/140 MH z units,
and 950–1950 MHz for L-Band units) is translated to an intermediate frequency (approx. 465 MHz
for L-Band), and then further translated to baseband using the carrier recovery VCO. This is a
complex mix, resulting in the signal once more being split into an in-phase (I) and a quadrature (Q)
component.
An AGC circuit maintains the desired signal level constant over a broad range. Following this, the I
and Q signals are sampled by high-speed (flash) A/D converters. All processing beyond this
conversion is purely digital, performing the functions of Nyquist filtering, carrier recovery, and
symbol timing recovery. The resultant demodulated signal is fed, in soft decision form, to the
selected FEC decoder (Turbo).
After decoding, the recovered clock and data pass to the IP Module where traffic is examined and
processed for four channels before it is delivered to the Ethernet port.
The demodulator signal processing functions are performed in two, large Field-Programmable Gate
Array (FPGA), which permits rapid implementation of changes, additions and enhancements in the
field. These signal-processing functions are controlled and monitored by a 32-bit RISC
microprocessor, which also controls all front panel indicators, serial and Ethernet interfaces.
As shown in the block diagrams depicted in Figure 1-3, the demodulator is physically comprised
of a single printed circuit board assembly, with integral Turbo FEC and IP router.