Status registers – GW Instek PEL-2000 Series Programming User Manual User Manual
Page 163
STATUS REGISTERS
163
B
IT
W
E
IG
H
T
1
2
4
8
OR
16
CONDITION
1
2
4
8
PTR/NTR
1
2
4
8
EVENT
1
2
4
8
ENABLE
OC
OV
OP
RV
OT
Protection
0
1
2
3
4
Bit position
B
IT
W
E
IG
H
T
1
2
4
8
16
EVENT
1
2
4
8
16
ENABLE
CH1
CH2
CH3
CH4
CH5
Channel
0
1
2
3
4
Bit position
32
64
128
32
64
128
CH6
CH7
CH8
5
6
7
B
IT
W
E
IG
H
T
1
2
4
8
OR
CONDITION
1
2
4
8
PTR/NTR
1
2
4
8
EVENT
1
2
4
8
ENABLE
OC
OV
OP
RV
Query
0
1
2
3
Bit position
OR
Questionable Status Registers
CH1 CH2 CH3 CH4 CH5
From
CH6 CH7 CH8
B
IT
W
E
IG
H
T
1
4
8
OR
Standard Event Status Registers
16
EVENT
1
4
8
16
ENABLE
OPC
N.U.
QYE
DDE
EXE
Message
0
1
2
3
4
Bit position
32
32
CME
N.U.
N.U.
5
6
7
Data
Data
Output Queue
Data
BIT
WEIGHT
4
8
16
STATUS BYTE
N.U.
N.U.
CSUM QUES
MAV
Status
0
1
2
3
4
Bit position
32
ESB
MSS
N.U.
5
4
8
OR
16
2
3
4
Bit position
32
5
Service Request Generation Register
CSUM QUES
MAV
ESB
BIT
WEIGHT
Service
Request
Generation
7
6
64
Status Byte Register
OR
Service
Request
Generation
Channel Summary Registers
32
G/N
5
64
UVP
6
N.U.
7-15
16
32
64
16
32
64
16
32
64
16
OT
4
32
G/N
5
64
UVP
6
N.U.
7-15
16
32
64
16
32
64
16
32
64
Channel Status Registers (Channel X)