Altera JESD204B IP - Manual (Page 101)

Figure 5-7: User Data Format that Feeds into the Transport Layer and Output to the Link Layer
Converter Device, MxN bits, S Samples per Single Converter per Frame Cycle
MSB LSB
Converter 0,
M0
Sample 0
S0
Sample 1
S1
Sample S - 1
S[S - 1]
Converter i,
Mi
Sample 0
S0
Sample S - 1
S[S - 1]
Converter M - 1,
M[M - 1]
Sample 0
S0
Sample S - 1
S[S - 1]
M0S0 M0S1 M0S[S - 1] MiS0 MiS[S - 1] M[M - 1]S0
M[M - 1]
S[S - 1]
M[M - 1]
S[S - 1]
M[M - 1]S0 MiS[S - 1] MiS0 M0S[S - 1] M0S1 M0S0
Control bits Appended to Each Sample (CF = 0)
Word1,
M0S1 + C1
Word0,
M0S0 + C0
NG1,
Word1 + T
NG0,
Word0 + T
Octet F-2,
F[F - 2]
Octet F-1,
F[F - 1]
Octet 2,
F2
Octet 3,
F3
Octet 0,
F0
Octet 1,
F1
F0 F1 F2 F3 F[F - 2] F[F - 1]
Frame Clock to Link Clock Adaptor
F4 F5 F6 F7
F0 F1 F2 F3
Lane 0, L0
Altera JESD IP Core
Lane L - 1, L[L - 1]
Sample from the
converter is N bits wide
The user reorders the
data so that M0S0 is
at the LSB and M[M -
1]S[S - 1] is at the
MSB. Data out from
the RX has tthe same
orientation, M0S0 at
the LSB.
Add the control bit
Add the tail bit to
N’ = 16
The transport layer
reshuffles the data in
big endian format
F = 8 in this example 2nd link clock
1st link clock
32 bits of data per
lane in the link clock
domain is packed to
the JESD204B IP core
This Region of the Transport Layer
Is in the Frame Clock Domain
This Region of the Transport Layer
Is in the Link Clock Domain
1
2
3
4
5
Application layer or user logic's
Avalon-ST data bus
The following tables show examples of data mapping for L=4, F=1, 2, 4, 8 and M*S=2, 4, 8, 16. The
configurations that the transport layer support are not limited to these examples.
Table 5-6: Data Mapping for F=1, L=4
F = 1
Supported M
and S
M*S=2 for F=1, L=4
F=1 supports either (case1: M=1, S=2) or (case2: M=2, S=1)
5-20 TX Path Data Remapping
UG-01142
2015.05.04
Altera Corporation JESD204B IP Core Design Guidelines
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