Altera JESD204B IP User Manual
Page 76
Signal
Width
Direction
Description
jesd204_rx_avs_clk
1
Input
The Avalon-MM interface clock signal. This clock
is asynchronous to all the functional clocks in the
JESD204B IP core. The JESD204B IP core can
handle any cross clock ratio and therefore the
clock frequency can range from 75 MHz to 125
MHz.
jesd204_rx_avs_rst_n
1
Input
This reset is associated with the
jesd204_rx_avs_
clk
signal. This reset is an active low signal. You
can assert this reset signal asynchronously but
must deassert it synchronously to the
jesd204_
rx_avs_clk
signal. After you deassert this signal,
the CPU can configure the CSRs.
jesd204_rx_avs_
chipselect
1
Input
When this signal is present, the slave port ignores
all Avalon-MM signals unless this signal is
asserted. This signal must be used in combination
with read or write. If the Avalon-MM bus does not
support chip select, you are recommended to tie
this port to 1.
jesd204_rx_avs_
address[]
8
Input
For Avalon-MM slave, the interconnect translates
the byte address into a word address in the address
space so that each slave access is for a word of data.
For example, address = 0 selects the first word of
the slave and address = 1 selects the second word
of the slave.
jesd204_rx_avs_
writedata[]
32
Input
32-bit data for write transfers. The width of this
signal and the
jesd204_rx_avs_readdata[31:0]
signal must be the same if both signals are present.
jesd204_rx_avs_read
1
Input
This signal is asserted to indicate a read transfer.
This is an active high signal and requires the
jesd204_rx_avs_readdata[31:0]
signal to be in
use.
jesd204_rx_avs_write
1
Input
This signal is asserted to indicate a write transfer.
This is an active high signal and requires the
jesd204_rx_avs_writedata[31:0]
signal to be
in use.
jesd204_rx_avs_
readdata[]
32
Output
32-bit data driven from the Avalon-MM slave to
master in response to a read transfer.
UG-01142
2015.05.04
Receiver
4-39
JESD204B IP Core Functional Description
Altera Corporation